1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a wordline voltage generation circuit and a nonvolatile memory device including the wordline voltage generation circuit.
2. Description of Related Art
A flash memory device typically includes an array of memory cells constituted by floating gate transistors. The array of memory cells includes strings of floating gate transistors, also called NAND strings. Each of the floating gate transistors is serially connected between a string selection transistor and a ground selection transistor. A plurality of wordlines are arranged to intersect the NAND strings. Each of the wordlines is connected to a control gate of a corresponding floating gate transistor of the NAND string. The floating gate transistors are the memory cells, which are erased to have a voltage of, for example, −3 V. To program a memory cell, a high voltage of, for example, 20 V, is applied to a wordline of the memory cell selected during a given time. While a program voltage of the selected memory is increased, program voltages of non-selected memory cells do not change.
An incremental step pulse programming (ISPP) method is used to substantially prevent a program error, for example, wherein the non-selected memory cells are programmed during the programming operation. In the ISPP method, a program voltage Vpgm to be applied to a selected wordline gradually increases from a low voltage to a high voltage during a program loop. The program voltage Vpgm takes the form of a pulse that has a given width and increases by ΔVpgm as compared to a prior pulse. The given width and ΔVpgm substantially prevent a program error due to a sudden increase in the program voltage. The distribution of the program voltage (e.g., the difference between a height of the start program voltage and a target program voltage) of the memory cell to be programmed is set to control the distribution of the program voltage. Circuits for generating a program voltage according to the ISPP scheme are disclosed in U.S. Pat. No. 5,642,309 entitled “AUTO-PROGRAM CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE.”
FIG. 1 is a graph illustrating a change in a wordline voltage when a programming operation is performed using an ISPP scheme. In this document, a wordline voltage and a program voltage are used synonymously.
Referring to FIG. 1, a program voltage of the first program loop is called a start program voltage Vpgm1, and a program voltage of the m-th program loop is called a target program voltage VpgmM. As program loops of a program cycle repeat, the program voltage Vpgm gradually increases from the start program voltage Vpgm1 by a predetermined increment ΔVpgm. When a program voltage of a corresponding cell to be programmed reaches the limit of a program voltage of a target cell, it is determined that the corresponding cell has been programmed. When a non-programmed cell exists, the program loop increases. When it is determined that all the cells have been programmed, the program loop is interrupted. When all the cells are not programmed within the predetermined number of times of the program, it is determined that the corresponding block has failed to be programmed.
Memory device characteristics demanded by users have diversified with the advances in miniaturization and integration. Some users want a memory device that can be rapidly programmed, while other users attach importance to the distribution of the program voltage of the programmed memory cell. As the program operation progresses, the program voltage of the programmed cell increases by an increment ΔVpgm set in each of program loops. Accordingly, the increment ΔVpgm of the program voltage needs to be reduced to increase the distribution of the program voltage of the programmed memory cell. The increment ΔVpgm needs to be increased to rapidly performing the program operation. As described above, the increment ΔVpgm of the program voltage needs to be set differently according to the user demands.
A method of changing the increment ΔVpgm of the program voltage operates by changing a program step code. In this method, the program step code is changed to increase resistance of a voltage divider by two steps (2ΔR) rather than by one step (ΔR), thereby doubling the increment ΔVpgm of the program voltage. A separate circuit is needed for changing the program step code, resulting in an increased circuit area and a more complicated structure. Also, the increment of the program voltage can be changed only by an integer multiple of a default value. Therefore, it can be difficult to satisfy the user demands by the above method.
FIGS. 2A and 2B illustrate a case where the increment ΔVpgm of the wordline voltage is changed without a change in the program step code. FIG. 2A is a graph illustrating a change in the wordline voltage when an increment thereof is set to a value smaller than ΔVpgm. FIG. 2B is a graph illustrating a change in the wordline voltage when the increment is set to a value larger than ΔVpgm. As illustrated in FIGS. 2A and 2B, when the increment ΔVpgm of the wordline voltage is changed, the start program voltage and the target program voltage are changed accordingly.
Referring to FIG. 2A, a dashed line represents the wordline voltage for the increment ΔVpgm. A solid line represents the wordline voltage when the increment of the wordline voltage is reduced from ΔVpgm to ΔVpgm/K (where K is a real number larger than 1). As illustrated in FIG. 2A, when the increment of the program voltage is reduced, the distribution width of the memory cell decreases, and the program loop width is increased for the target program voltage of the cell reducing the program speed. When the increment ΔVpgm of the program voltage is reduced by 1/K, the start program voltage ΔVpgm1 and the target program voltage ΔVpgmM are reduced accordingly. Referring to FIG. 2A, the start program voltage is reduced from Vpgm1 to Vpgm1′, and the target program voltage is reduced from VpgmM to VpgmM′. The program loop is increased to obtain the target program voltage of the cell to program the cell. The reduced program voltage increment ΔVpgm/K, the reduced start program voltage Vpgm1′, and the reduced target program voltage VpgmM′ cause the program loop to increase, and the program voltage of the programmed memory cell to be distributed over a smaller range than that of the target program voltage distribution. This results in an under program problem where a cell is not programmed within the program loop.
Referring to FIG. 2B, a dashed line represents the wordline voltage when the increment ΔVpgm of the wordline voltage remains unchanged. A solid line represents the wordline voltage when the increment of the wordline voltage is increased from ΔVpgm to K×ΔVpgm (where K is a real number larger than 1). To enhance the program speed in the ISPP scheme, the increment ΔVpgm of the program voltage is set to a larger value, K×ΔVpgm, as illustrated in FIG. 2B. As the increment ΔVpgm of the program voltage is increased, a program loop width for obtaining the target program voltage is reduced, enhancing the program speed while a range of the program voltage of the programmed cell is extended. The start program voltage Vpgm1 and the target program voltage VpgmM are also increased as the increment ΔVpgm of the program voltage is increased by K times. Referring to FIG. 2B, the start program voltage is increased from Vpgm1 to Vpgm1″, and the target program voltage is increased from VpgmM to VpgmM″. The increased start program voltage Vpgm1″ and the increased target program voltage VpgmM″ cause an over program problem where the program voltage of the programmed memory cell is distributed over a higher range than that of the target program voltage distribution.
As described above, to satisfy the user demands, a need exists for a system and method to be able to set the increment of the wordline voltage to a random value. Also, to prevent the under program problem and the over program problem, a need exists for a memory device capable of maintaining the start program voltage or the target program voltage.